name description adress --- ----------- ------ ACC acummulator E0 B B register F0 DPTR datapointer DPH datapointer highbyte 83 DPL datapointer lowbyte 82 IE interrupt enable A8 IP interrupt priority B8 P0 port 0 80 P1 port 1 90 P2 port 2 A0 P3 port 3 B0 PCON power control 87 PSW program status word D0 SBUF serial databuffer 99 SCON serial controller 98 SP stack pointer 81 TCON timer control 88 T2CON timer 2 control C8 TH0 timer high 0 8C TH1 timer high 1 8D TL0 timer low 0 8A TL1 timer low 1 8B TMOD timer mode 8919950419IE
bit description symbol --- ----------- ------ 76543210 0------- disable all interrupts EA 1------- enable all interrupt control bits EA -x------ reserved --0----- timer 2 interrupt disabled ET2 --1----- timer 2 interrupt enabled ET2 ---0---- disable serial port interrupt ES ---1---- enable serial port interrupt ES ----0--- disable timer 1 interrupt ET1 ----1--- enable timer 1 interrupt ET1 -----0-- disable external interrupt 1 EX1 -----1-- enable external interrupt 1 EX1 ------0- disable timer 0 interrupt ET0 ------1- enable timer 0 interrupt ET0 -------0 disable external interrupt 0 EX0 -------1 enable external interrupt 0 EX0IP
bit description symbol --- ----------- ------ 76543210 x------- reserved -x------ reserved --1----- priority of timer 2 PT2 ---1---- priority of serial port interrupt PS ----1--- priority of timer 1 interrupt PT1 -----1-- priority of external interrupt 1 PX1 ------1- priority of timer 0 interrupt PT0 -------1 priority of external interrupt 0 PX0PSW
bit description symbol --- ----------- ------ 76543210 x------- carry flag CY -x------ auxiliary carry flag AC --x----- general purpose status flag F0 ---x---- register bank select bit 1 RS1 ----x--- register bank select bit 0 RS0 -----x-- overflow flag OV ------x- user definable -------x parity of accumulator PSCON
bit description symbol --- ----------- ------ 76543210 x------- serial port mode SM0 -x------ serial port mode SM1 00------ mode 0 : shift register f_osc/1201 01------ mode 1 : 8-bit UART variable10 10------ mode 2 : 9-bit UART f_osc/64 of f_osc/3211 11------ mode 3 : 9-bit UART variable --x----- enable multiprocessorfeature in SM2 modes 2 & 3, RI will not be activated if RB8=0 & SM2=1 in mode 1 RI will not be activated if stop bit was invalid & SM2=1 SM2 should be 0 in mode 0 ---0---- disable reception REN ---1---- enable reception REN ----x--- in modes 2&3 9-th bit tx TB8 -----x-- in modes 2&3 9-th bit rx RB8 mode1 ; if SM2=0 RB8=stop bit value mode0 ; not used ------x- tx interrupt flag TI mode0 : set by 8-th bit time other modes : set by beginning of stop bit, clear by software . -------x rx interrupt flag RI hardware set at the end of 8th bit time in mode 0, halfway trough the stop bit time in other modes (see SM2) clear by software.TCON
bit description symbol --- ----------- ------ 76543210 x------- timer 1 overflow flag TF1 -0------ timer 1 off TR1 -1------ timer 1 on TR1 --0----- timer 0 overflow flag TF0 set on overflow, reset on jump to interrupt routine ---0---- timer 0 off TR0 ---1---- timer 0 on TR0 ----x--- interrupt 1 edge flag IE1 set on external interrupt detect reset after interrupt processed -----0-- interrupt 1 low level trigger IT1 -----1-- interrupt 1 falling edge trigger IT1 ------x- interrupt 0 edge flag (see IE1) IE0 -------x interrupt 0 triggercontrol (see IT1) IT0T2CON
bit description symbol --- ----------- ------ 76543210 x------- timer 2 overflow flag TF2 -x------ timer 2 external flag EXF2 --x----- receive clock flag RCLK ---x---- transmit clock flag TCLK ----x--- timer 2 external enable flag EXEN2 -----0-- stop timer TR2 -----1-- start timer ------0- internal timer C/T2 ------1- external timer -------x capture / reload flag CP/RL2TMOD
bit description symbol --- ----------- ------ 76543210 0-------| t/c enabled via TR1 GATE 1-------|t t/c enabled via INT1 + TR1 -0------|i timer T/C -1------|m counter T/C --00----|e TL1 serves as 5-bit prescaler M1,M0 --01----|r 16-bit t/c TH1 & TL1 are cascaded --10----|1 8-bit reloader, valTH1 is loaded in TL1 when TL1 overflows --11----| t/c 1 is stopped 0-------| t/c enabled via TR0 GATE 1-------|t t/c enabled via INT0 + TR0 -0------|i timer T/C -1------|m counter T/C --00----|e TL0 serves as 5-bit prescaler M1,M0 --01----|r 16-bit t/c TH0 & TL0 are cascaded --10----|0 8-bit reloader, valTH0 is loaded in TL0 when TL0 overflows ------11| TL0 is an 8-bit t/c controlled by Timer 0 controlbits TH0 is an 8-bit t/c controlled by Timer 1 controlbits
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mgeysken@innet.be