The EISA Bus This file is intended to provide a basic functional overview of the EISA Bus, so that hobbyists and ametuers can design their own EISA compatible cards. It is not intended to provide complete coverage of the EISA standard. It is also not intended to provide coverage of standard ISA bus cycles, and will not detail ISA bus operations unless they pertain to the EISA extensions. The EISA standard may be obtained from the following sources: BCPR Services (Texas) 1-713-251-4770 Global Engineering Documents (Colorado) 1-800-854-7179 EISA is an acronym for Extended Industry Standard Architecture. It is an extension of the ISA architecture, which is a standardized version of the bus originally developed by IBM for their PC computers. EISA is upwardly compatible, which means that cards originally designed for the 8 bit IBM bus (often referred to as the XT bus) and cards designed for the 16 bit bus (referred to as the AT bus, and also as the ISA bus), will work in an EISA slot. EISA specific cards will not work in an AT or an XT slot. The EISA connector uses multiple rows of connectors. The upper row is the same as a regular ISA slot, and the lower row contains the EISA extension. The slot is keyed so that ISA cards cannot be inserted to the point where they connet with the EISA signals. Connector Signal Descriptions Component Side A1: *CHCHK E1: *CMD F1: GND B1: GND A2: SD7 E2: *START F2: +5 B2: *RESDRV A3: SD6 E3: EXRDY F3: +5 B3: +5 A4: SD5 E4: *EX32 F4: reserved B4: IRQ2 A5: SD4 E5: GND F5: reserved B5: -5 A6: SD3 E6: (key) F6: (key) B6: DRQ2 A7: SD2 E7: *EX16 F7: reserved B7: -12 A8: SD1 E8: *SLBURST F8: reserved B8: *NOWS A9: SD0 E9: *MSBURST F9: +12 B9: +12 A10: CHRDY E10: W/R F10: M/IO B10: GND A11: AEN E11: GND F11: *LOCK B11: *SMWTC A12: SA19 E12: reserved F12: reserved B12: *SMRDC A13: SA18 E13: reserved F13: GND B13: *IOWC A14: SA17 E14: reserved F14: reserved B14: *IORC A15: SA16 E15: GND F15: *BE3 B15: *DAK3 A16: SA15 E16: (key) F16: (key) B16: DRQ3 A17: SA14 E17: *BE1 F17: *BE2 B17: *DAK1 A18: SA13 E18: *LA31 F18: *BE0 B18: DRQ1 A19: SA12 E19: GND F19: GND B19: *REFRESH A20: SA11 E20: *LA30 F20: +5 B20: BCLK A21: SA10 E21: *LA28 F21: *LA29 B21: IRQ7 A22: SA9 E22: *LA27 F22: GND B22: IRQ6 A23: SA8 E23: *LA25 F23: *LA26 B23: IRQ5 A24: SA7 E24: GND F24: *LA24 B24: IRQ4 A25: SA6 E25: (key) F25: (key) B25: IRQ3 A26: SA5 E26: LA15 F26: LA16 B26: *DAK2 A27: SA4 E27: LA13 F27: LA14 B27: TC A28: SA3 E28: LA12 F28: +5 B28: BALE A29: SA2 E29: LA11 F29: +5 B29: +5 A30: SA1 E30: GND F30: GND B30: OSC A31: SA0 E31: LA9 F31: LA10 B31: GND G1: LA7 H1: LA8 C1: *SBHE G2: GND H2: LA6 D1: *M16 C2: LA23 G3: LA4 H3: LA5 D2: *IO16 C3: LA22 G4: LA3 H4: +5 D3: IRQ10 C4: LA21 G5: GND H5: LA2 D4: IRQ11 C5: LA20 G6: (key) H6: (key) D5: IRQ12 C6: LA19 G7: SD17 H7: SD16 D6: IRQ13 C7: LA18 G8: SD19 H8: SD18 D7: IRQ14 C8: LA17 G9: SD20 H9: GND D8: *DAK0 C9: *MRDC G10: SD22 H10: SD21 D9: DRQ0 C10: *MWTC G11: GND H11: SD23 D10: *DAK5 C11: SD8 G12: SD25 H12: SD24 D11: DRQ5 C12: SD9 G13: SD26 H13: GND D12: *DAK6 C13: SD10 G14: SD28 H14: SD27 D13: DRQ65 C14: SD11 G15: (key) H15: (key) D14: *DAK7 C15: SD12 G16: GND H16: SD29 D15: DRQ7 C16: SD13 G17: SD30 H17: +5 D16: +5 C17: SD14 G18: SD31 H18: +5 D17: *MASTER16 C18: SD15 G19: *MREQx H19: *MAKx D18: GND * Active Low +5, -5, +12, -12: Power supplies. -5 is often not implimented. AEN: Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from responding to the I/O command lines during a DMA transfer. BALE: Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle. Memory devices should latch the LA bus on the falling edge of BALE. BCLK: Bus Clock, 33% Duty Cycle. Frequency Varies. 8.33 MHz is specified as the maximum, but many systems allow this clock to be set to 10 MHz and higher. BE(x): Byte Enable. Indicates to the slave device which bytes on the data bus contain valid data. A 16 bit transfer would assert BE0 and BE1, for example, but not BE2 or BE3. CHCHK: Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the cpu. CHRDY: Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may then set it high again when it is ready to end the bus cycle. Holding this line low for too long can cause problems on some systems. CHRDY and NOWS should not be used simultaneously. This may cause problems with some bus controllers. CMD: Command Phase. This signal indicates that the current bus cycle is in the command phase. After the start phase (see START), the data is transferred during the CMD phase. CMD remains asserted from the falling edge of START until the end of the bus cycle. DAKx: DMA Acknowledge. DRQx: DMA Request. EX16: EISA Slave Size 16. This is used by the slave device to inform the bus master that it is capable of 16 bit transfers. EX32: EISA Slave Size 32. This is used by the slave device to inform the bus master that it is capable of 32 bit transfers. EXRDY: EISA Ready. If this signal is asserted, the cycle will end on the next rising edge of BCLK. The slave device drives this signal low to insert wait states. IO16: I/O size 16. Generated by a 16 bit slave when addressed by a bus master. IORC: I/O Read Command line. IOWC: I/O Write Command line. IRQx: Interrupt Request. IRQ2 has the highest priority. Interrupt lines on the EISA bus may be level triggered (which allows sharing of interrupt lines) or edge triggered, which is required for ISA compatibility. LAxx: Latchable Address lines. LA17 through LA23 are the same as for the ISA bus. LA24 through LA31 are unique to the EISA extension. These combine with the SA bus to form the complete address. LOCK: Asserting this signal prevents other bus masters from requesting control of the bus. MAKx: Master Acknowledge for slot x: Indicates that the bus master request (MREQx) has been granted. MASTER16: 16 bit bus master. Generated by the ISA bus master when initiating a bus cycle. M/IO: Memory/Input-Output. This is used to indicate whether the current bus cycle is a memory or an I/O operation. M16: Memory Access, 16 bit MRDC: Memory Read Command line. MREQx: Master Request for Slot x: This is a slot specific request for the device to become the bus master. MSBURST: Master Burst. The bus master asserts this signal in response to SLBURST. This tells the slave device that the bus master is also capable of burst cycles. MWTC: Memory Write Command line. NOWS: No Wait State. Used to shorten the number of wait states generated by the default ready timer. This causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and both signals should not be active simultaneously. OSC: Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies. REFRESH: Refresh. Generated when the refresh logic is bus master. RESDRV: This signal goes low when the machine is powered up. Driving it low will force a system reset. SA0-SA19: System Address Lines. SBHE: System Bus High Enable, tristate. Indicates a 16 bit data transfer. SD0-SD16: System Data lines. SLBURST: Slave Burst. The slave device uses this to indicate that it is capable of burst cycles. The bus master will respond with MSBURST if it is also capable of burst cycles. SMRDC: Standard Memory Read Command line. Indicates a memory read in the lower 1 MB area. SMWTC: Standard Memory Write Commmand line. Indicates a memory write in the lower 1 MB area. START: Start Phase. This signal is low when the current bus cycle is in the start phase. Address and M/IO signals are decoded during this phase. Data is transferred during the command phase (indicated by CMD). TC: Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete. W/R: Write or Read. Used to indicate if the current bus cycle is a read or a write operation. EISA Bus Cycle (1 wait state shown): Ts Tc Tc ___ ___ ___ ___ ___ BCLK |___| |___| |___| |___| |__ ________________ LAxx ---<________________>---[1]----------- ___________ W/R,M/IO --------<___________>----------------- ___________ BEx --------<___________>----------------- _______________ ______ CMD |_______________| _______ ______________________ START |_______| ___________ __________________ EX16/EX32,IO16 |_______| ______________ ____________ EXRDY |__________| _______________________ SDxx (Write) -----------<_______________________>-- _____ SDxx (Read) ---------------------------<_____>----- [1] The address for the next cycle may appear before the current cycle has completed. When address pipelining is active, the address may appear on the bus before the transfer cycle begins. This allows devices to decode the address early, which helps to boost performance. The EISA cycle is divided into a start phase (represented by Ts above) and a command phase (represented by Tc). During the start phase, the address on the LA bus and all of the command lines (BEx, MEM/IO, W/R) are valid, and will remain valid until halfway through the first command cycle. Address information should be latched on the trailing edge of START. Upon decoding the address and command lines, the device drives EX16 or EX32 low. IO16 should also be pulled low. The device also pulls EXRDY low, and releases it when it is ready to complete the cycle. EXRDY is sampled at the midpoint of Tc. EISA Burst transfer: Ts Tc Tc Tc Tc ___ ___ ___ ___ ___ ___ ___ BCLK |___| |___| |___| |___| |___| |___| |___ _________________ ______ ______ ______ LAxx ---<_________________><______><______><______>--------- ____________________________________ W/R,M/IO --------<____________________________________>--------- ____________ ______ ______ ______ BEx --------<____________><______><______><______>--------- _______________ _______ CMD |_______________________________| _______ _______________________________________ START |_______| ___________ _______ EX16/EX32,IO16 |___________________________________| _____________ _________ SLBURST |_______________________________| ___________________ ___________ MSBURST |_______________________| ____________ ______ ______ ______ SDxx (Write) -----------<____________><______><______><______>----- ___ ___ ___ ___ SDxx (Read) ---------------------<___>---<___>---<___>---<___>---- In this example, EXRDY is held high (no wait states). Wait states will be inserted if EXRDY is low at the midpoint of Tc. A burst transfer is done when the slave device asserts SLBURST during the EISA transfer cycle. The master asserts MSBURST to acknowledge that the transfer will be a burst transfer. The burst cycle continues until MSBURST is sampled high at the end of Tc. Interrupts: EISA has two control ports added to help overcome the limits of ISA's edge triggered interrupts (which do not easily allow the sharing of IRQs). By setting or clearing bits in these control ports, each IRQ can be individually set as edge or level triggered. When the system powers up, these ports are set with all IRQs edge triggered (all IRQ bits cleared), which maintains ISA compatibility. When the control bit is set to a 1 for the corresponding IRQ, it becomes level triggered, active low, allowing it to be much more easily shared. I/O ports 04D0 (hex) and 04D1 are used for the master and slave interrupt controllers, respectively. The registers are called ELCR (Edge/Level Control Register). 0 = edge triggered, active high 1 = level triggered, active low I/O Port 04D0: Bit 7 = IRQ7 6 = IRQ6 5 = IRQ5 4 = IRQ4 3 = IRQ3 2 = always set to zero (cascade to slave interrupt controller) 1 = IRQ1 (Keyboard Controller, always set to zero) 0 = IRQ0 (System Timer, always set to zero) I/O Port 04D1: Bit 7 = IRQ15 6 = IRQ14 5 = IRQ13 (Coprocessor/DMAC, always set to zero) 4 = IRQ12 3 = IRQ11 2 = IRQ10 1 = IRQ9 0 = IRQ8 (Real Time Clock Alarm, always set to zero) EISA Bus Masters: (under construction) (C) Copyright 1996 by Mark Sokos. This file may be freely copied and distributed, as long as no fee is charged.The latest version of this file may be found at: http://www.gl.umbc.edu~/msokos1 E-mail questions or comments to msokos1@gl.umbc.edu. References: "Eisa System Architecture, 2nd Edition" by Tom Shanley and Don Anderson ISBN 0-201-40995-X